Development of a Universal Networked Timer at NSTX
Authors: P. Sichta, J. Dong, J.E. Lawson, G. Oliaro, and J. Wertenbaker
Date of PPPL Report: September 2005
Presented at: the Twenty-First Symposium on Fusion Engineering (SOFE2005), 26 - 29 September 2005, Knoxville, Tennessee USA.
A new Timing and Synchronization System component, the Universal Networked Timer (UNT), is under development at the National Spherical Torus Experiment (NSTX). The UNT is a second-generation multifunction timing device that emulates the timing functionality and electrical interfaces originally provided by various CAMAC modules. Using Field Programmable Gate Array (FPGA) technology, each of the UNT's eight channels can be dynamically programmed to emulate a specific CAMAC module type. The timer is compatible with the existing NSTX timing and synchronization system and will also support a (future) clock system with extended performance. To assist system designers and collaborators, software will be written to integrate the UNT with EPICS, MDSplus, and LabVIEW. This paper will describe the timing capabilities, hardware design, programming/software support, and the current status of the Universal Networked Timer at NSTX.